Specification Sheet

Datasheet, Volume 2 of 2 265
GFXVTBAR Registers
Bit
Range
Default &
Access
Field Name (ID): Description
63:59
0h
RO
Reserved (RSVD): Reserved.
58
0h
RO
SL64KP: A value of 1 in this field indicates 64-KByte page size is supported for
second-level translation.
57
0h
ROV
FL64KP: A value of 1 in this field indicates 64-KByte page size is supported for first-
level translation.
56
1h
ROV
FL1GP: A value of 1 in this field indicates 1-GByte page size is supported for first-level
translation.
55
1h
RO
DRD:
0: Hardware does not support draining of DMA read requests.
1: Hardware supports draining of DMA read requests.
54
1h
RO
DWD:
0: Hardware does not support draining of DMA write requests.
1: Hardware supports draining of DMA write requests.
53:48
0h
RO
MAMV: The value in this field indicates the maximum supported value for the Address
Mask (AM) field in the Invalidation Address register (IVA_REG) and IOTLB Invalidation
Descriptor (iotlb_inv_dsc).
This field is valid only when the PSI field in Capability register is reported as Set.
47:40
0h
RO
NFR: Number of fault recording registers is computed as N+1, where N is the value
reported in this field.
Implementations should support at least one fault recording register (NFR = 0) for
each remapping hardware unit in the platform.
The maximum number of fault recording registers per remapping hardware unit is
256.
39
0h
RO
PSI:
0: Hardware supports only domain and global invalidates for IOTLB
1: Hardware supports page selective, domain and global invalidates for IOTLB.
Hardware implementations reporting this field as set are recommended to support a
Maximum Address Mask Value (MAMV) value of at least 9.
38
0h
RO
Reserved (RSVD): Reserved.
37:34
3h
ROV
SLLPS: This field indicates the super page sizes supported by hardware.
A value of 1 in any of these bits indicates the corresponding super-page size is
supported. The super-page sizes corresponding to various bit positions within this field
are:
0: 21-bit offset to page frame (2MB)
1: 30-bit offset to page frame (1GB)
2: 39-bit offset to page frame (512GB)
3: 48-bit offset to page frame (1TB)
Hardware implementations supporting a specific super-page size should support all
smaller super-page sizes, i.e. only valid values for this field are 0001b, 0011b, 0111b,
1111b.
33:24
40h
RO
FRO: This field specifies the location to the first fault recording register relative to the
register base address of this remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the address
for the first fault recording register is calculated as X+(16*Y).
23
0h
RO
Reserved (RSVD): Reserved.
22
1h
RO
ZLR:
0: Indicates the remapping hardware unit blocks (and treats as fault) zero length DMA
read requests to write-only pages.
1: Indicates the remapping hardware unit supports zero length DMA read requests to
write-only pages.
DMA remapping hardware implementations are recommended to report ZLR field as
Set.