Specification Sheet

Datasheet, Volume 2 of 2 245
MCHBAR Registers
7.84 CONFIG—Offset 5F3Ch
This register is used to indicate the Nominal Configurable TDP ratio available for this
specific SKU. System BIOS should use this value while building the _PSS table if the
feature is enabled.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:4
0h
RO
Reserved (RSVD): Reserved.
3:0
0h
RW
REQ_DATA: These 4 bits are the data for the request. The only possible request type
is MC frequency request. The encoding of this field is the 133/266 MHz multiplier for
DCLK/QCLK: Binary Dec DCLK Equation DCLK Freq QCLK Equation QCLK Freq
000b 0d -----------------------------MC PLL – shutdown--------------------------------
…
0011b 3d 3*133.33 400.00 MHz 3*266.67 MHz 800.00 MHz
0100b 4d 4*133.33 533.33 MHz 4*266.67 MHz 1066.67 MHz
0101b 5d 5*133.33 666.67 MHz 5*266.67 MHz 1333.33 MHz
0110b 6d 6*133.33 800.00 MHz 6*266.67 MHz 1600.00 MHz
0111b 7d 7*133.33 933.33 MHz 7*266.67 MHz 1866.67 MHz
1000b 8d 8*133.33 1066.67 MHz 8*266.67 MHz 2133.33 MHz
…
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5F3Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
TDP_RATIO
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0h
RO
Reserved (RSVD): Reserved.
7:0
0h
RO_V
TDP_RATIO: Nominal TDP level ratio to be used for this specific processor (in units of
100 MHz).
Note: A value of 0 in this field indicates invalid/undefined TDP point