Specification Sheet
MCHBAR Registers
244 Datasheet, Volume 2 of 2
7.83 PCU_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PCU—
Offset 5E00h
This register allows BIOS to request Memory Controller clock frequency.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RW1S
ENABLE_PCIE_NDA_PG: This bit indicates if PCIE-NDA power-gating is enabled
(disabled by default). Hardware looks at this bit after RST_CPL is set and decides
whether or not to power-gate the PEG controllers and AFE. If it is asserted and all
devices are disabled (post CPL), hardware will power-gate the devices.
Note 1: This mode does not survive warm-reset, i.e. on a warm reset NDA mode is
canceled and power to PEG controllers is resumed.
Note 2: If checked only on CPL, no need to check also PCIE_ENUMERATION_DONE.
2
0h
RW
C7_ALLOWED: BIOS/driver will set this bit when only discrete graphics is being used
and the PCIe lanes will be down. BIOS/driver will clear this bit when discrete graphics
is being used.
THIS FIELD IS OBSOLETE. NOT USED ANYWHERE!!! (Nov-2013)
1
0h
RW
PCIE_ENUMERATION_DONE: This will be set after PCIe enumeration is done. This
bit will be read by hardware. If it is set, hardware will look at the following register
bits:
MPVTDTRK_CR_DEVEN_0_0_0_PCI
Bit Bit Name
1 D1F2EN
2 D1F1EN
3 D1F0EN
If all of these bits are set to a 0x0, this means that there is nothing connected to the
PEG devices and the Gen3 PLL can be shut off.
Note: implicit assumption - this bit is asserted prior to (or with) asserting RST_CPL.
0
0h
RW
RST_CPL: This bit is set by BIOS to indicate to the Processor Power management
function that it has completed to set up all PM relevant configuration and allow
Processor Power management function to digest the configuration data and start
active PM operation.
It is expected that this bit will be set just before BIOS transfer of control to the OS.
0b: Not ready
1b: BIOS PM configuration complete
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5E00h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
REQ_DATA