Specification Sheet
MCHBAR Registers
242 Datasheet, Volume 2 of 2
7.80 RP—Offset 5998h
This register contains the maximum base frequency capability for the Integrated GFX
Engine (GT).
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5998h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
RPN_CAP
RP1_CAP
RP0_CAP
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0h
RO
Reserved (RSVD): Reserved.
23:16
0h
ROS
RPN_CAP: This field indicates the maximum RPN base frequency capability for the
Integrated GFX Engine (GT). Values are in units of 50 MHz.
15:8
0h
ROS
RP1_CAP: This field indicates the maximum RP1 base frequency capability for the
Integrated GFX Engine (GT). Values are in units of 50 MHz.
7:0
0h
ROS
RP0_CAP: This field indicates the maximum RP0 base frequency capability for the
Integrated GFX Engine (GT). Values are in units of 50 MHz.