Specification Sheet

Datasheet, Volume 2 of 2 241
MCHBAR Registers
7.79 RP—Offset 5994h
This register allows SW to limit the maximum base frequency for the Integrated GFX
Engine (GT) allowed during run-time.
Access Method
Default: FFh
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0h
RO
Reserved (RSVD): Reserved.
7:0
0h
RO_V
DATA: Temperature in degrees (C).
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5994h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RSVD
RPSTT_LIM
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0h
RO
Reserved (RSVD): Reserved.
7:0
FFh
RW
RPSTT_LIM: This field indicates the maximum base frequency limit for the Integrated
GFX Engine (GT) allowed during run-time.