Specification Sheet

Processor Configuration Register Definitions and Address Ranges
32 Datasheet, Volume 2 of 2
3. In the case of overlapping ranges with memory, the memory decode will be given
priority. This is an Intel
®
Trusted Execution Technology (Intel
®
TXT) requirement.
It is necessary to get Intel TXT protection checks, avoiding potential attacks.
4. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
5. Accesses to overlapped ranges may produce indeterminate results.
6. The only peer-to-peer cycles allowed below the Top of Low Usable memory
(register TOLUD) are DMI Interface to PCI Express VGA range writes. Peer-to-peer
cycles to the Processor Graphics VGA range are not supported.
Figure 2-2. System Address Range Example