Specification Sheet

Datasheet, Volume 2 of 2 229
MCHBAR Registers
7.65 DDR—Offset 58C8h
Per-DIMM throttle duration counters. These accumulate the duration (in absolute wall
clock time) that the iMC rank throttlers have been blocking memory traffic due to
OLTM/CLTM/EXTTS thermal status. Note that RAPL throttling is done at the channel
level, and thus is NOT included in these values.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:32
0h
RO
Reserved (RSVD): Reserved.
31:16
0h
ROS
DIMM1: Throttle duration of DIMM 1 on this channel, in units of 1/1024 seconds.
15:0
0h
ROS
DIMM0: Throttle duration of DIMM 0 on this channel, in units of 1/1024 seconds.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 58C8h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DIMM1 DIMM0
Bit
Range
Default &
Access
Field Name (ID): Description
63:32
0h
RO
Reserved (RSVD): Reserved.
31:16
0h
ROS
DIMM1: Throttle duration of DIMM 1 on this channel, in units of 1/1024 seconds.
15:0
0h
ROS
DIMM0: Throttle duration of DIMM 0 on this channel, in units of 1/1024 seconds.