Specification Sheet

Datasheet, Volume 2 of 2 31
Processor Configuration Register Definitions and Address Ranges
When running in Processor Graphics mode, processor initiated TileX/Tiley/linear reads/
writes to GMADR range are supported. Write accesses to GMADR linear regions are
supported from both DMI and PEG. GMADR write accesses to TileX and TileY regions
(defined using fence registers) are not supported from the DMI or the PEG port.
GMADR read accesses are not supported from either DMI or PEG.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express*, DMI, or to the Processor Graphics device (Processor
Graphics). In the absence of more specific references, cycle descriptions referencing
PCI should be interpreted as the DMI Interface/PCI, while cycle descriptions referencing
PCI Express or Processor Graphics are related to the PCI Express bus or the Processor
Graphics device respectively. The processor does not remap APIC or any other memory
spaces above TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the
appropriate value by BIOS. The remapbase/remaplimit registers remap logical accesses
bound for addresses above 4 GB onto physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges:
• Device 0:
— PXPEPBAR – PxP egress port registers. (4 KB window)
— MCHBAR – Memory mapped range for internal MCH registers. (32 KB window)
— DMIBAR –This window is used to access registers associated with the
processor/PCH Serial Interconnect (DMI) register memory range. (4 KB
window)
— GGC.GMS – Graphics Mode Select. Used to select the amount of main memory
that is pre-allocated to support the Processor Graphics device in VGA (non-
linear) and Native (linear) modes. (0 – 512 MB options).
— GGC.GGMS – GTT Graphics Memory Size. Used to select the amount of main
memory that is pre-allocated to support the Processor Graphics Translation
Table. (0 – 2 MB options).
• For each of the following device functions
• Device 2, Function 0: (Processor Graphics (Processor Graphics))
— IOBAR – I/O access window for Processor Graphics. Through this window
address/data register pair, using I/O semantics, the Processor Graphics and
Processor Graphics instruction port registers can be accessed. This allows
accessing the same registers as GTTMMADR. The IOBAR can be used to issue
writes to the GTTMMADR or the GTT Table.
— GMADR – Processor Graphics translation window (128 MB, 256 MB, 512 MB
window).
— GTTMMADR – This register requests a 4 MB allocation for combined Graphics
Translation Table Modification Range and Memory Mapped Range. GTTADR will
be at GTTMMADR + 2 MB while the MMIO base address will be the same as
GTTMMADR
The rules for the above programmable ranges are:
1. For security reasons, the processor will now positively decode (FFE0_0000h to
FFFF_FFFFh) to DMI. This ensures the boot vector and BIOS execute off the PCH.
2. ALL of these ranges should be unique and NON-OVERLAPPING. It is the BIOS or
system designer's responsibility to limit memory population so that adequate PCI,
PCI Express, High BIOS, PCI Express Memory Mapped space, and APIC memory
space can be allocated.