Specification Sheet

Datasheet, Volume 2 of 2 225
MCHBAR Registers
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
POLICY_FREE_THRESHOLD2 POLICY_FREE_THRESHOLD1
RSVD
ENABLE_THRESHOLD2_INTERRUPT
RSVD
ENABLE_THRESHOLD1_INTERRUPT
RSVD
ENABLE_OOS_TEMP_INTERRUPT
RSVD
ENABLE_2X_REFRESH_INTERRUPT
RSVD
ENABLE_HOT_INTERRUPT
RSVD
ENABLE_WARM_INTERRUPT
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0h
RW
POLICY_FREE_THRESHOLD2: A threshold temperature value used only for interrupt
generation. No iMC throttling or other actions should be directly affected by this value.
This only works when CLTM is enabled. This is an 8-bit unsigned value with variable
units/format/resolution (see the processor ECO 3156947). THRESHOLD1 and
THRESHOLD2 values and enables are fully independent from each other.
23:16
0h
RW
POLICY_FREE_THRESHOLD1: A threshold temperature value used only for interrupt
generation. No iMC throttling or other actions should be directly affected by this value.
This only works when CLTM is enabled. This is an 8-bit unsigned value with variable
units/format/resolution (see the processor ECO 3156947). THRESHOLD1 and
THRESHOLD2 values and enables are fully independent from each other.
15:11
0h
RO
Reserved (RSVD): Reserved.
10
0h
RW
ENABLE_THRESHOLD2_INTERRUPT: When set, interrupts will be generated on
both rising and falling transition of the hottest absolute DIMM temperature across the
POLICY_FREE_THRESHOLD2 value. This interrupt will never get triggered by hardware
in cases where CLTM is not enabled (i.e. does not work with OLTM). THRESHOLD1 and
THRESHOLD2 values and enables are fully independent from each other.
9
0h
RO
Reserved (RSVD): Reserved.
8
0h
RW
ENABLE_THRESHOLD1_INTERRUPT: When set, interrupts will be generated on
both rising and falling transition of the hottest absolute DIMM temperature across the
POLICY_FREE_THRESHOLD1 value. This interrupt will never get triggered by hardware
in cases where CLTM is not enabled (i.e. does not work with OLTM). THRESHOLD1 and
THRESHOLD2 values and enables are fully independent from each other.
7
0h
RO
Reserved (RSVD): Reserved.
6
0h
RW
ENABLE_OOS_TEMP_INTERRUPT: When set, interrupts will be generated on a
rising transition of hottest MR4 to 3'b111.
This interrupt will never get triggered by hardware in cases where MAD_CHNL.LPDDR
is zero or DISABLE_DRAM_TS is set.
5
0h
RO
Reserved (RSVD): Reserved.