Specification Sheet

MCHBAR Registers
224 Datasheet, Volume 2 of 2
7.59 DDR—Offset 589Ch
Per-DIMM temp/power thresholds used for CLTM/OLTM thermal status computation.
These values can impact iMC throttling and memory thermal interrupts.
Access Method
Default: FFFFh
7.60 DDR—Offset 58A0h
Enable bits and policy-free thresholds used for controlling memory thermal interrupt
generation.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 589Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RSVD
DIMM1 DIMM0
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15:8
FFh
RWS_L
DIMM1: HOT_THRESHOLD for DIMM1 on this channel.
7:0
FFh
RWS_L
DIMM0: HOT_THRESHOLD for DIMM0 on this channel.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 58A0h