Specification Sheet
MCHBAR Registers
220 Datasheet, Volume 2 of 2
7.54 DRAM—Offset 5888h
Defines the minimum required power consumption of each DDR channel, in order to
satisfy minimum memory bandwidth requirements for the platform. DDR RAPL should
never throttle below the levels defined here. It is the responsibility of BIOS to
comprehend the power consumption on each channel in order to write meaningful
values into this register.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:3
0h
RO
Reserved (RSVD): Reserved.
2:0
3h
RW
SCALEFACTOR: Defines the base DDR energy unit of 2^(-30-scalefactor) Joules. The
values are defined as follows:
0d0 = 3'b000 = 931.3pJ,
0d1 = 3'b001 = 465.7pJ,
0d2 = 3'b010 = 232.8pJ,
0d3 = 3'b011 = 116.4pJ,
0d4 = 3'b100 = 58.2pJ,
0d5 = 3'b101 = 29.1pJ,
0d6 = 3'b110 = 14.6pJ,
0d7 = 3'b111 = 7.3pJ.
The default reset value is 0d3 = 3'b011 = 116.4pJ.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5888h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
CH1
CH0
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15:8
0h
RW
CH1: Minimum power level (in format of 5.3 W) used to clip DDR RAPL power budget
for channel 1.
7:0
0h
RW
CH0: Minimum power level (in format of 5.3 W) used to clip DDR RAPL power budget
for channel 0.