Specification Sheet
Datasheet, Volume 2 of 2 219
MCHBAR Registers
7.53 DRAM—Offset 5884h
Defines the base energy unit for DDR energy values in iMC command energy con-
figuration regs, iMC rank energy counters (used for OLTM and Memory RAPL), OLTM
thresholds, etc.
Access Method
Default: 3h
3:2
0h
RW
REFRESH_2X_MODE: These bits are read by reset hardware and later broadcast
(together with the thermal status) into the iMC cregs that control 2x refresh modes.
When DRAM is hot, it accumulates bits errors more quickly. The iMC refresh
mechanism is how those errors get prevented and corrected (using ECC). Thus in
order to maintain an acceptable overall error rate, the refresh rate needs to increase
with temperature. This is a very coarse grain mechanism for accomplishing that. A
value of 00 means the iMC 2x refresh is disabled. A value of 01 means that the iMC will
enable 2x refresh whenever thermal status is WARM or HOT. A value of 10 means the
iMC will enable 2x refresh only when HOT. The value 11 is illegal, and will trigger an
assertion in the iMC (BIOS should not do this). This field is ignored for LPDDR when
DISABLE_DRAM_TS is zero, in which case refresh rates in the MC are controlled by
MR4 coming directly from DIMMs.
1
0h
RW
CLTM_ENABLE: A value of 1 means CLTM (Closed Loop Thermal Management)
hardware algorithm will be used to compute the memory thermal status (which will be
written to the iMC). Note that OLTM and CLTM modes are mutex, so if both
OLTM_ENABLE and CLTM_ENABLE are set, the OLTM_ENABLE will be ignored and CTLM
mode will be active. BIOS should enable CLTM whenever DIMM thermal sensor data is
available and memory thermal management is desired.
0
0h
RW
OLTM_ENABLE: A value of 1 means OLTM (Open Loop Thermal Management)
hardware algorithm will be used to compute the memory thermal status (which will be
written to the iMC). Note that OLTM and CLTM modes are mutex, so if both
OLTM_ENABLE and CLTM_ENABLE are set, the OLTM_ENABLE will be ignored and CTLM
mode will be active. BIOS should enable OLTM in case of thermal sensor data absence,
but memory thermal management is desired. Obviously lack of real temperature data
means this mode will be somewhat conservative, and may result in the iMC throttling
more often than necessary. Thus, for performance reasons, CLTM is preferred on
systems with available DIMM thermal sensor data.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5884h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
RSVD
SCALEFACTOR