Specification Sheet

MCHBAR Registers
218 Datasheet, Volume 2 of 2
7.52 DDR—Offset 5880h
Mode control bits for DDR power and thermal management features.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5880h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DDR4_SKIP_REFRESH_EN
DISABLE_DRAM_TS
PDWN_CONFIG_CTL
LOCK_PTM_REGS_PCU
EXTTS_ENABLE
REFRESH_2X_MODE
CLTM_ENABLE
OLTM_ENABLE
Bit
Range
Default &
Access
Field Name (ID): Description
31:9
0h
RO
Reserved (RSVD): Reserved.
8
0h
RW
DDR4_SKIP_REFRESH_EN: DDR4 DRAM supports temperature controlled refresh
and self refresh. The temperature controlled refresh is essentially DRAM controls to
skip some refresh issued by the host when temperature is low enough. When this bit is
set and MAD_CHNL.DDR4=1, MC will enable DRAM's TC refresh mode aka skip refresh
mode. hardware uses MAD_CHNL.DDR4 and PTM_CTL.DDR4_SKIP_REFRESH_EN to
determine whether to support DDR thermal interrupt for refresh rate change. BIOS is
responsible to configure this bit and is ZERO by default.
7
0h
RW
DISABLE_DRAM_TS: When this bit is zero and MAD_CHNL.LPDDR=1, hardware will
use DDR MR4 for DIMM thermal status purposes. Otherwise, hardware will ignore MR4
data and use the legacy CLTM/OLTM/EXTTS algorithms for computing DIMM thermal
status.
6
0h
RW
PDWN_CONFIG_CTL: This bit determined whether BIOS or hardware will control
DDR powerdown modes and idle counter (via programming the PM_PDWN_config regs
in iMC). When clear, hardware will manage the modes based on either core P-states or
IA32_ENERGY_PERFORMANCE_BIAS MSR value (when enabled). When set, BIOS is in
control of DDR CKE mode and idle timer value, and hardware algorithm does not run.
5
0h
RW_KL
LOCK_PTM_REGS_PCU: When set, several PCU registers related to DDR power/
thermal management all become unwritable (writes will be silently ignored). List of
registered locked by this bit is: DDR_WARM_THRESHOLD_CH*,
DDR_HOT_THRESHOLD_CH*, DDR_WARM_BUDGET_CH*, DDR_HOT_BUDGET_CH*,
(note that RAPL regs, such as RAPL_LIMIT, are NOT included as those have separate
lock bit). Note that BIOS should complete its writes to all of the locked registers prior
to setting this bit, since it can only be reset via uncore reset.
4
0h
RW
EXTTS_ENABLE: When clear (default), hardware ignores the EXTTS (external
thermal status) indication which is obtained from the PCH (via PM_SYNC). When set,
the value from EXTTS is used only when it is hotter than the thermal status reported
by OLTM/CLTM algorithm (or used all of the time if neither of those modes is enabled).