Specification Sheet

MCHBAR Registers
216 Datasheet, Volume 2 of 2
7.48 PKG—Offset 5838h
Sum the cycles of active GT
Access Method
Default: 0h
7.49 PKG—Offset 5840h
Sum the cycles of overlap time between any IA cores and GT
Access Method
Default: 0h
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 5838h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA
Bit
Range
Default &
Access
Field Name (ID): Description
63:0
0h
ROV
DATA: RO, This counter increments whenever GT slices or un slices are active and in
C0 state. Counter rate is the Max Non-Turbo frequency (same as TSC)
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 5840h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATA
Bit
Range
Default &
Access
Field Name (ID): Description
63:0
0h
ROV
DATA: This counter increments whenever GT slices or un slices are active and in C0
state and in overlap with one of the IA cores that is active and in C0 state. Counter
rate is the Max Non-Turbo frequency (same as TSC)