Specification Sheet
Datasheet, Volume 2 of 2 213
MCHBAR Registers
7.45 PACKAGE—Offset 5820h
Thermal Limitation Interrupt Control. Hardware will read this information before
generating a thermal interrupt.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
38:12
0h
RO
VTVC0BAR: This field corresponds to bits 38 to 12 of the base address DMI/PEG VC0
configuration space. BIOS will program this register resulting in a base address for a
4KB block of contiguous memory address space. This register ensures that a naturally
aligned 4KB space is allocated within the first 512GB of addressable memory space.
System Software uses this base address to program the DMI/PEG VC0 register set. All
the Bits in this register are locked in LT mode.
0
0h
RO
VTVC0BAREN: VC0BAR is disabled and does not claim any memory
1: VC0BAR memory mapped accesses are claimed and decoded appropriately. This bit
will remain 0 if VTd capability is disabled.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5820h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMPERATURE_AVERAGING_TIME_WINDOW
POWER_INT_ENABLE
THRESHOLD_2_INT_ENABLE
THRESHOLD_2_REL_TEMP
THRESHOLD_1_INT_ENABLE
THRESHOLD_1_REL_TEMP
RSVD
OUT_OF_SPEC_INT_ENABLE
RSVD
PROCHOT_INT_ENABLE
LOW_TEMP_INT_ENABLE
HIGH_TEMP_INT_ENABLE