Specification Sheet
MCHBAR Registers
212 Datasheet, Volume 2 of 2
7.44 NCDECS_CR_VTDPVC0BAR_0_0_0_MCHBAR_NCU—Of
fset 5410h
This is the base address for the DMI/PEG VC0 configuration space. There is no physical
memory within this 4KB window that can be addressed. The 4KB reserved by this
register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the
DMI/PEG VC0 configuration space is disabled and should be enabled by writing a 1 to
VC0BAREN.
Access Method
Default: 0h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
GFXVTBAR
RSVD
GFXVTBAREN
Bit
Range
Default &
Access
Field Name (ID): Description
38:12
0h
RO
GFXVTBAR: This field corresponds to bits 38 to 12 of the base address GFX-VT
configuration space. BIOS will program this register resulting in a base address for a
4KB block of contiguous memory address space. This register ensures that a naturally
aligned 4KB space is allocated within the first 512GB of addressable memory space.
System Software uses this base address to program the GFX-VT register set. All the
Bits in this register are locked in LT mode.
0
0h
RO
GFXVTBAREN: GFX-VTBAR is disabled and does not claim any memory 1: GFX-VTBAR
memory mapped accesses are claimed and decoded appropriately This bit will remain
0 if VTd capability is disabled.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 5410h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
VTVC0BAR
RSVD
VTVC0BAREN