Specification Sheet

Datasheet, Volume 2 of 2 211
MCHBAR Registers
7.42 Self refresh configuration Register (PM)—Offset
5060h
Self refresh mode control register - defines if and when DDR can go into SR
Access Method
Default: 10200h
7.43 NCDECS_CR_GFXVTBAR_0_0_0_MCHBAR_NCU—
Offset 5400h
This is the base address for the Graphics VT configuration space. There is no physical
memory within this 4KB window that can be addressed. The 4KB reserved by this
register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the
GFX-VT configuration space is disabled and should be enabled by writing a 1 to GFX-
VTBAREN.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5060h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
RSVD
SR_Enable
Idle_timer
Bit
Range
Default &
Access
Field Name (ID): Description
31:17
0h
RO
Reserved (RSVD): Reserved.
16
1h
RW_LV
SR_Enable: enables or disables self-refresh mechanism. In order to allow SR, both
SREF_en bit should be set and SREF_exit signal should be cleared. PM_SREF_config
may be updated in run-time
15:0
200h
RW_LV
Idle_timer: This value is used when the SREF_enable field is set. It defines the
number of cycles that there should not be any transaction in order to enter self-
refresh.
Supported range is 512 to 64K-1
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 5400h