Specification Sheet

MCHBAR Registers
210 Datasheet, Volume 2 of 2
7.41 WR data count (DRAM)—Offset 5054h
Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all
channels). All requests result in 64-byte data transfers from DRAM. Use for accurate
memory bandwidth calculations.
Access Method
Default: 0h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
count
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_LV
count: Number of accesses
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5054h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
count
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_LV
count: Number of accesses