Specification Sheet

Datasheet, Volume 2 of 2 209
MCHBAR Registers
7.39 Request count from IO (DRAM)—Offset 5048h
Counts every read/write request entering the Memory Controller to DRAM (sum of all
channels) from all IO sources (e.g. PCIe, Display Engine, USB audio, etc.). Each partial
write request counts as a request incrementing this counter. However same-cache-line
partial write requests are combined to a single 64-byte data transfers from DRAM.
Therefore multiplying the number of requests by 64-bytes will lead to inaccurate IO
memory bandwidth. The inaccuracy is proportional to the number of same-cache-line
partial writes combined.
Access Method
Default: 0h
7.40 RD data count (DRAM)—Offset 5050h
Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all
channels). All requests result in 64-byte data transfers from DRAM. Use for accurate
memory bandwidth calculations.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_LV
count: Number of accesses
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5048h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
count
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_LV
count: Number of accesses
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5050h