Specification Sheet
MCHBAR Registers
208 Datasheet, Volume 2 of 2
combined to a single 64-byte data transfers from DRAM. Therefore multiplying the
number of requests by 64-bytes will lead to inaccurate GT memory bandwidth. The
inaccuracy is proportional to the number of same-cache-line partial writes combined.
Access Method
Default: 0h
7.38 Request count from IA (DRAM)—Offset 5044h
Counts every read/write request (demand and HW prefetch) entering the Memory
Controller to DRAM (sum of all channels) from IA. Each partial write request counts as
a request incrementing this counter. However same-cache-line partial write requests
are combined to a single 64-byte data transfers from DRAM. Therefore multiplying the
number of requests by 64-bytes will lead to inaccurate IA memory bandwidth. The
inaccuracy is proportional to the number of same-cache-line partial writes combined.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5040h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
count
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_LV
count: Number of accesses
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5044h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
count