Specification Sheet

Datasheet, Volume 2 of 2 207
MCHBAR Registers
7.36 MCDECS_CR_MRC_REVISION_0_0_0_MCHBAR_MCMA
IN—Offset 5034h
Scheduler configuration.
Access Method
Default: 0h
7.37 Request count from GT (DRAM)—Offset 5040h
Counts every read/write request entering the Memory Controller to DRAM (sum of all
channels) from the GT engine. Each partial write request counts as a request
incrementing this counter. However same-cache-line partial write requests are
9:8
0h
RW_L
DLW: DLW: DIMM L width of DDR chips
00: X8 chips
01: X16 chips
10: X32 chips
11: Reserved
7:6
0h
RO
Reserved (RSVD): Reserved.
5:0
0h
RW_L
DIMM_L_SIZE: Size of DIMM L in 1GB multiples
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5034h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
REVISION
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_L
REVISION: BIOS MRC Revision.
7:0 = Build #
15:8 = Revision
23:16 = Minor
31:24 = Major