Specification Sheet

MCHBAR Registers
206 Datasheet, Volume 2 of 2
7.35 Address decode DIMM parameters (MAD)—Offset
5010h
This register defines channel DIMM characteristics - number of DIMMs, number of
ranks, size and type.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5010h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DS8Gb
DSNOR
DSW
RSVD
DIMM_S_SIZE
RSVD
DL8Gb
DLNOR
DLW
RSVD
DIMM_L_SIZE
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0h
RO
Reserved (RSVD): Reserved.
27
0h
RW_L
DS8Gb: Defines whether DIMM S is built from 8Gb DRAM modules.
0: Not 8Gb
1: 8Gb
26
0h
RW_L
DSNOR: DIMM S number of ranks
0: 1 Rank
1: 2 Ranks
25:24
0h
RW_L
DSW: DSW: DIMM S width of DDR chips
00: X8 chips
01: X16 chips
10: X32 chips
11: Reserved
23:22
0h
RO
Reserved (RSVD): Reserved.
21:16
0h
RW_L
DIMM_S_SIZE: Size of DIMM S in 1GB multiples
15:12
0h
RO
Reserved (RSVD): Reserved.
11
0h
RW_L
DL8Gb: Defines whether DIMM L is built from 8Gb DRAM modules.
0: Not 8Gb
1: 8Gb
10
0h
RW_L
DLNOR: DIMM L number of ranks
0: 1 Rank
1: 2 Ranks