Specification Sheet

Datasheet, Volume 2 of 2 29
Processor Configuration Register Definitions and Address Ranges
From a configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices
internal to the processor and the PCH appear to be on PCI Bus 0.
Table 2-3. S-Processor and X-Series Processor PCI Devices and Functions
Description
DID
Device Function
S-Processor Line
X-Series
Processor Line
Package LGA1151 LGA2066
Segment Desktop HEDT
HOST and DRAM Controller
Dual Core - 590Fh
Quad Core - 906E9h 0 0
Quad Core -591Fh
PCI Express* Controller (x16 PCIe) 5901h 5901h 1 0
PCI Express* Controller (x8 PCIe) 5905h 5905h 1 1
PCI Express* Controller (x4 PCIe) 5909h 5909h 1 2
Processor Graphics
5902h - GT1
N/A 2 0
5912h - GT2
Imaging Unit N/A N/A 5 0
Gaussian Mixture Model 1911h 1911h 8 0