Specification Sheet

Datasheet, Volume 2 of 2 205
MCHBAR Registers
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0h
RO
Reserved (RSVD): Reserved.
27
0h
RW_L
DS8Gb: Defines whether DIMM S is built from 8Gb DRAM modules.
0: Not 8Gb
1: 8Gb
26
0h
RW_L
DSNOR: DIMM S number of ranks
0: 1 Rank
1: 2 Ranks
25:24
0h
RW_L
DSW: DSW: DIMM S width of DDR chips
00: X8 chips
01: X16 chips
10: X32 chips
11: Reserved
23:22
0h
RO
Reserved (RSVD): Reserved.
21:16
0h
RW_L
DIMM_S_SIZE: Size of DIMM S in 1GB multiples
15:12
0h
RO
Reserved (RSVD): Reserved.
11
0h
RW_L
DL8Gb: Defines for DDR3 whether DIMM L is built from 8Gb DRAM modules.
0: Not 8Gb
1: 8Gb
For non DDR3, this field should be set to 0.
10
0h
RW_L
DLNOR: DIMM L number of ranks
0: 1 Rank
1: 2 Ranks
9:8
0h
RW_L
DLW: DLW: DIMM L width of DDR chips
00: X8 chips
01: X16 chips
10: X32 chips
11: Reserved
7:6
0h
RO
Reserved (RSVD): Reserved.
5:0
0h
RW_L
DIMM_L_SIZE: Size of DIMM L in 1GB multiples