Specification Sheet

Datasheet, Volume 2 of 2 203
MCHBAR Registers
7.33 Address decoder intra channel configuration
register (MAD)—Offset 5008h
This register holds parameters used by the DRAM decode stage.
Access Method
Default: 0h
4
0h
RW_L
RI: Rank interleaving enable bit
0: Disabled
1: Enabled
3:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW_L
DIMM_L_MAP: Virtual DIMM L mapping to physical DIMM
0: DIMM0
1: DIMM1
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5008h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
HORI_ADDR
RSVD
HORI
RSVD
ECC
RSVD
EIM
RSVD
RI
RSVD
DIMM_L_MAP
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RO
Reserved (RSVD): Reserved.
30:28
0h
RW_L
HORI_ADDR: High Order Rank Interleave Address. Specifies which address bit 20-27
to use as the rank interleave bit
000: bit 20
001: bit 21
...
111: - bit 27
27:25
0h
RO
Reserved (RSVD): Reserved.
24
0h
RW_L
HORI: High order rank interleaving enable bit
0: Disabled
1: Enabled
High Order Rank Interleave (HORI) is mutually exclusive with Rank Interleave (RI)
23:14
0h
RO
Reserved (RSVD): Reserved.