Specification Sheet
Datasheet, Volume 2 of 2 201
MCHBAR Registers
7.31 Address decoder inter channel configuration
register (MAD)—Offset 5000h
This register holds parameters used by the channel decode stage. It defines virtual
channel L mapping, as well as channel S size. Also defined is the DDR type installed in
the system (DDR4 or DDR3).
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 5000h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
CH_S_SIZE
RSVD
CH_L_MAP
RSVD
DDR_TYPE
Bit
Range
Default &
Access
Field Name (ID): Description
31:19
0h
RO
Reserved (RSVD): Reserved.
18:12
0h
RW_L
CH_S_SIZE: Channel S size in multiplies of 1GB (min. rank size in the processor).
Needed for channel decode stage.
Supports range of 0GB - 64GB.
11:5
0h
RO
Reserved (RSVD): Reserved.
4
0h
RW_L
CH_L_MAP: Channel L mapping to physical channel.
0: Channel0
1: Channel1
3:2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
RW_L
DDR_TYPE: DDR_TYPE - defines the DDR type in system:
00: DDR4
01: DDR3
10: LPDDR3