Specification Sheet

MCHBAR Registers
198 Datasheet, Volume 2 of 2
7.28 Power Management DIMM Activate Energy (PM)—
Offset 4E68h
This register defines the combined energy contribution of activate and precharge
commands. Each 8-bit field corresponds to an integer multiple of the base DRAM
command energy for that DIMM. There are 2 8-bit fields, one per DIMM.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:14
0h
RO
Reserved (RSVD): Reserved.
13:8
0h
RW_L
DIMM1_PD_ENERGY: This register defines the energy consumed by DIMM1 for one
clock cycle when the DIMM is idle with cke off
7:6
0h
RO
Reserved (RSVD): Reserved.
5:0
0h
RW_L
DIMM0_PD_ENERGY: This register defines the energy consumed by DIMM0 for one
clock cycle when the DIMM is idle with cke off
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4E68h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
DIMM1_ACT_ENERGY DIMM0_ACT_ENERGY
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15:8
0h
RW_L
DIMM1_ACT_ENERGY: This register defines the combined energy contribution of
activate and precharge commands.
7:0
0h
RW_L
DIMM0_ACT_ENERGY: This register defines the combined energy contribution of
activate and precharge commands.