Specification Sheet

MCHBAR Registers
196 Datasheet, Volume 2 of 2
7.25 Refresh timing parameters (TC)—Offset 4E3Ch
Refresh timing parameters
Access Method
Default: B41004h
7.26 Power Management DIMM Idle Energy (PM)—
Offset 4E60h
This register defines the energy of an idle DIMM with CKE on. Each 6-bit field
corresponds to an integer multiple of the base DRAM command energy for that DIMM.
There are 2 6-bit fields, one per DIMM.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4E3Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
RSVD
tRFC
tREFI
Bit
Range
Default &
Access
Field Name (ID): Description
31:26
0h
RO
Reserved (RSVD): Reserved.
25:16
B4h
RW_L
tRFC: Time of refresh - from beginning of refresh until next ACT or refresh is allowed
(in DCLK cycles, default is 180)
15:0
1004h
RW_L
tREFI: defines the average period between refreshes, and the rate that tREFI counter
is incremented (in DCLK cycles, default is 4100)
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4E60h