Specification Sheet
MCHBAR Registers
194 Datasheet, Volume 2 of 2
7.23 MCSCHEDS_CR_TC_ODT_0_0_0_MCHBAR—Offset
4C70h
ODT timing related parameters.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4C70h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
tCWL
tCL
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:26
0h
RO
Reserved (RSVD): Reserved.
25:21
6h
RW_L
tCWL: Holds DDR timing parameter tCWL (sometimes refereed to as tWCL).Write
command to data delay in DCLK cycles
Supported range is 4-20 (maximum is for 1N mode and tCAL=0)
For LPDDR3 the minimum supported value is 4 if Dec_WRD=0 5 and if Dec_WRD=1
For DDR3/4 the minimum supported value is 5 if Dec_WRD=0 6 and if Dec_WRD=1
20:16
5h
RW_L
tCL: Holds DDR timing parameter tCL.Read command to data delay in DCLK cycles.
Supported range is 5-31.
15:0
0h
RO
Reserved (RSVD): Reserved.