Specification Sheet
Datasheet, Volume 2 of 2 193
MCHBAR Registers
7.22 PM—Offset 4C40h
This register defines the power-down (CKE-off) operation - power-down mode, and idle
timers associated with power down entry
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4C40h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
dis_cke_tt
TT_idle_counter
Global_PD
Slow_Exit
PPD
APD
PDWN_idle_counter
Bit
Range
Default &
Access
Field Name (ID): Description
31:25
0h
RO
Reserved (RSVD): Reserved.
24
0h
RW_L
dis_cke_tt:
1'b0: CKE TT is enabled. When throttling is asserted TT_idle_counter value is loaded
into the CKE counter. The CKE FSM will be forced to the countdown state upon
activation of throttling. When a rank becomes non-isoch-empty the CKE FSM will turn
on if currently off.
1'b1: CKE TT is defeatured.
23:16
0h
RW_L
TT_idle_counter: Amount of cycles to wait before going to PD when thermal
throttling is enabled
15
0h
RW_L
Global_PD: Power down entry and exit conditions are determined globally for the
whole channel and not on a per rank basis
14
0h
RW_L
Slow_Exit: Indicate if DDR (applicable only for DDR3/DDR4) that it is in slow exit
mode so when exiting PPD the MC should wait tXPDLL before sending a CAS command
and not tXP
13
0h
RW_L
PPD: When rank is idle close all pages and go to PPD. If both APD and PPD are set and
not all banks are closed when idle first go to APD then once all page idle timers expire
go out of APD, issue a PREALL and then power down to PPD.
Note that enabling both APD+PPD requires page table idle timers not to be disabled by
SCHED_CBIT_0_0_0_MCHBAR.dis_pt_it for proper operation This field is controller by
hardware unless DDR_PTM_CTL_0_0_0_MCHBAR_PCU.PDWN_CONFIG_CTL is set
12
0h
RW_L
APD: Put rank in APD when idle.
This field is controller by hardware unless
DDR_PTM_CTL_0_0_0_MCHBAR_PCU.PDWN_CONFIG_CTL is set
11:0
0h
RW_L
PDWN_idle_counter: This defines the rank idle period in DCLK cycles that causes
power-down entrance.
This field is controller by hardware unless
DDR_PTM_CTL_0_0_0_MCHBAR_PCU.PDWN_CONFIG_CTL is set