Specification Sheet

MCHBAR Registers
186 Datasheet, Volume 2 of 2
7.15 Refresh timing parameters (TC)—Offset 463Ch
Refresh timing parameters
Access Method
Default: B41004h
Bit
Range
Default &
Access
Field Name (ID): Description
31:25
23h
RW_L
tREFIx9: Maximum time allowed between refreshes to a rank (in intervals of 1024
DCLK cycles). Should be programmed to 8.9*tREFI/1024 (to allow for possible delays
from ZQ or isoc).
24:16
0h
RO
Reserved (RSVD): Reserved.
15:12
9h
RW_L
Refresh_panic_wm: tREFI count level in which the refresh priority is panic (default
is 9). The Maximum value for this field is 9.
11:8
8h
RW_L
Refresh_HP_WM: tREFI count level that turns the refresh priority to high (default is
8)
7:0
Fh
RW_L
OREF_RI: Rank idle period that defines an opportunity for refresh, in DCLK cycles
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 463Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
RSVD
tRFC
tREFI
Bit
Range
Default &
Access
Field Name (ID): Description
31:26
0h
RO
Reserved (RSVD): Reserved.
25:16
B4h
RW_L
tRFC: Time of refresh - from beginning of refresh until next ACT or refresh is allowed
(in DCLK cycles, default is 180)
15:0
1004h
RW_L
tREFI: defines the average period between refreshes, and the rate that tREFI counter
is incremented (in DCLK cycles, default is 4100)