Specification Sheet

Datasheet, Volume 2 of 2 185
MCHBAR Registers
7.14 Refresh parameters (TC)—Offset 4638h
Refresh parameters
Access Method
Default: 4600980Fh
10:8
0h
RO
ODT_write_duration: Controls the length of the ODT pulse for write commands.
Default is 6 DCLK cycles (BL/2 + 2)
000: 6 DCLK cycles
001: 7 DCLK cycles
010: 8 DCLK cycles
011: 9 DCLK cycles
100: 10 DCLK cycles
101: 11 DCLK cycles
110: 12 DCLK cycles
111: 13 DCLK cycles
6:4
0h
RO
ODT_Read_Delay: Controls delay from RD-CAS to ODT assertion in DCLK cycles
(Typical Programming = tCL-tCWL).
Note 1: All RD->RD and RD->WR restrictions should be greater than or equal to this
field value.
Note 2: odt_read_delay + odt_read_duration should not be programmed to less than
tCL-
2:0
0h
RO
ODT_read_duration:. Controls the length of the ODT pulse for read commands.
Default is 6 DCLK cycles (BL/2 +2)
000: 6 DCLK cycles
001: 7 DCLK cycles
010: 8 DCLK cycles
011: 9 DCLK cycles
100: 10 DCLK cycles
101: 11 DCLK cycles
110: 12 DCLK cycles
111: 13 DCLK cycles
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4638h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1
tREFIx9
RSVD
Refresh_panic_wm
Refresh_HP_WM
OREF_RI