Specification Sheet

MCHBAR Registers
184 Datasheet, Volume 2 of 2
7.13 MCHBAR_CH0_CR_TC_ODT_0_0_0_MCHBAR—
Offset 4470h
ODT timing related parameters
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4470h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ODT_Always_Rank0
tAONPD
tCWL
tCL
Write_Early_ODT
ODT_Write_Delay
RSVD
ODT_write_duration
RSVD
ODT_Read_Delay
RSVD
ODT_read_duration
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RO
ODT_Always_Rank0: Indicate that ODT should always be multiplexed out on
ODT[0], to be used for LPDDR3 only
30:26
0h
RO
tAONPD: Holds DDR timing parameter tAONPD. Supported range is 4-31.
25:21
0h
RO
tCWL: Holds DDR timing parameter tCWL (sometimes referred to as tWCL). Write
command to data delay in DCLK cycles. Supported range is 4-20 (maximum is for 1N
mode and tCAL=0) For LPDDR3 the minimum supported value is 4 if Dec_WRD=0 and
5 if Dec_WRD=1. For DDR3/4, the minimum supported value is 5 if Dec_WRD=0 and 6
if Dec_WRD=1.
20:16
0h
RO
tCL: Holds DDR timing parameter tCL. Read command to data delay in DCLK cycles.
Supported range is 5-31.
15
0h
RO
Write_Early_ODT: When this bit is set, the MC is will send one extra cycle of ODT
prior to the write command. In this mode the ranks that will be terminated on this
early cycle are selected according to the SC_ODT_MATRIX_0_0_0_MCHBAR control
register.
14:12
0h
RO
ODT_Write_Delay: Controls delay from WR-CAS to ODT assertion in DCLk cycles
(Typical Programming = 0).