Specification Sheet

Datasheet, Volume 2 of 2 183
MCHBAR Registers
22:20
0h
RO
reset_delay: Inserts an N Dclk delay ranging from 0 to 7 after the N to 1 Reset on
Cmd is triggered.
19:16
0h
RO
reset_on_command: The N:1 logic can be triggered to insert a bubble and reset the
N:1 logic after a programmable delay from a command after a PRE/ACT/RD/WR CMD.
This allows one to synchronize the N:1 logic periodically to ensure the correct worst
case pattern between victim and aggressor occurs when training the command bus.
Reset N to 1 Logic on a WR (bit 16) Reset N to 1 Logic on a RD (bit 17) Reset N to 1
Logic on a ACT (bit 18) Reset N to 1 Logic on a PRE (bit 19)
15
0h
RO
LPDDR_2N_CS_MRW: When sending an MRW command via the MRH for LPDDR
drive the CSb for two DCLK cycles
14:12
0h
RO
tCPDED: Holds DDR timing parameter tCPDED. Power down to command bus tri-state
delay in DCLK cycles. Supported range is 1-7 in 1N mode.
11:10
0h
RO
x8_device: DIMM is made out of X8 devices LSB is for DIMM 0, MSB is for DIMM 1.
9:8
0h
RO
Address_mirror: DIMM routing causes address mirroring LSB is for DIMM 0, MSB is
for DIMM 1.
6:4
0h
RO
N_to_1_ratio: When using N:1 command stretch mode, every how many B2B valid
command cycles a bubble is required Supported range is 1 to 7
3:2
0h
RO
CMD_stretch: Command stretch mode:
00: 1N
01: 2N
10: 3N
11: N:1
1:0
0h
RO
DRAM_technology: DRAM technology:
00: DDR4
01: DDR3
10: LPDDR3
11: Illegal
Bit
Range
Default &
Access
Field Name (ID): Description