Specification Sheet

MCHBAR Registers
182 Datasheet, Volume 2 of 2
7.12 MCHBAR_CH0_CR_SC_GS_CFG_0_0_0_MCHBAR—
Offset 441Ch
Scheduler configuration
Access Method
Default: 0h
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 441Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
tCAL
ddr_probeless_low_frequency
enable_odt_matrix
ck_to_cke
cmd_3st
reset_delay
reset_on_command
LPDDR_2N_CS_MRW
tCPDED
x8_device
Address_mirror
RSVD
N_to_1_ratio
CMD_stretch
DRAM_technology
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0h
RO
tCAL: For DDR4, holds tCAL value. Supported values: 0 (CAL mode disabled), 3-5
(CAL mode enabled, value is the delay in DCLK cycles from CSb to command).
Updating this field is required only after sending MRS to MR4 enabling/disabling CAL
mode before any other command is sent to DRAM.
TC_MR4_shaddow_0_0_0_MCHBAR should be updated with the correct value of tCAL
once its value changes.
28
0h
RO
ddr_probeless_low_frequency: This bit controls whether the DDR probeless logic
uses DDR_TX_DELAY_LOW or DDR_TX_DELAY_HIGH for the internal delay of the write
data. If MRC supports two training frequencies, this bit should be set when training at
the low frequency.
27
0h
RO
enable_odt_matrix: When bit is set, the ranks that are used for terminating when
giving read/write requests are selected according to SC_ODT_MATRIX control register
and not according to the default behavior.
26:24
0h
RO
ck_to_cke: When working with LPDDR when CKE is low we also turn off the CKe
buffers. The LPDDR specification requires starting the CK toggling two DCLK cycles
before re-asserting CKE. The field defines the number of DCLK cycles from
CKoutputEnable assert on power down exit to CKE assert as the DDRIO can delay the
CK pins differently than CKE so a different value is required to get two DCLK cycles of
CK toggling before CKE rise. Typically this field should be programmed to 3 if
(CLK_pi+CLK_logicdelay)-(CKE_pi+CKE_logicdelay) is less than 1 QCLK. Otherwise, it
should be programmed to 4 supported range is 2-7.
23
0h
RO
cmd_3st: Defines when command and address bus is driving.
0: Drive when channel is active. Tri-stated when all ranks are in CKE-off or when
memory is in SR or deeper.
1: Command bus is always driving. When no new valid command is driven, previous
command and address is driven