Specification Sheet
Datasheet, Volume 2 of 2 181
MCHBAR Registers
7.11 MCHBAR_CH1_CR_TC_PRE_0_0_0_MCHBAR—
Offset 4400h
DDR timing constraints related to PRE commands
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4400h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
tWRPRE
RSVD
tRDPRE
RSVD
tRAS
tRPab
tRP
Bit
Range
Default &
Access
Field Name (ID): Description
30:24
0h
RO
tWRPRE: Holds DDR timing parameter tWRPRE. WR to PRE same bank minimum
delay in DCLK cycles.
Note: tWRRD_sg+tRDPRE should be greater than or equal to tWRPRE Supported
range is 23-95.
19:16
0h
RO
tRDPRE: Holds DDR timing parameter tRDPRE. RD to PRE same bank minimum delay
in DCLK cycles. Supported range is 6-15
14:8
0h
RO
tRAS: Holds DDR timing parameter tRAS. ACT to PRE same bank minimum delay in
DCLK cycles. Supported range is 28-64.
7:6
0h
RO
tRPab: Holds the value of tRPab-tRPpb for LPDDR3 in DCLK cycles LPDDR3 reuiqres a
longer time from PREAL to ACT vs. PRE to ACT, the offset between the two should be
programmed to this field. When using DDR3/DDR4 this field should be programmed to
0. Supported range is 0-3.
5:0
0h
RO
tRP: Holds DDR timing parameter tRP (and tRCD). PRE to ACT same bank minimum
delay in DCLK cycles. ACT to CAS (RD or WR) same bank minimum delay in DCLK
cycles. For LPDDR3 this field should hold tRPpb (and tRCD) values. Supported range is
8-63.