Specification Sheet
MCHBAR Registers
176 Datasheet, Volume 2 of 2
7.6 Power Management DIMM Idle Energy (PM)—
Offset 4260h
This register defines the energy of an idle DIMM with CKE on. Each 6-bit field
corresponds to an integer multiple of the base DRAM command energy for that DIMM.
There are two 6-bit fields, one per DIMM.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4260h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
DIMM1_IDLE_ENERGY
RSVD
DIMM0_IDLE_ENERGY
Bit
Range
Default &
Access
Field Name (ID): Description
31:14
0h
RO
Reserved (RSVD): Reserved.
13:8
0h
RW_L
DIMM1_IDLE_ENERGY: This register defines the energy consumed by DIMM1 for
one clock cycle when the DIMM is idle with cke on
7:6
0h
RO
Reserved (RSVD): Reserved.
5:0
0h
RW_L
DIMM0_IDLE_ENERGY: This register defines the energy consumed by DIMM0 for
one clock cycle when the DIMM is idle with cke on.