Specification Sheet

MCHBAR Registers
172 Datasheet, Volume 2 of 2
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0h
RO
tCAL: For DDR4, holds tCAL value. Supported values: 0 (CAL mode disabled), 3-5
(CAL mode enabled, value is the delay in DCLK cycles from CSb to command).
Updating this field is required only after sending MRS to MR4 enabling/disabling CAL
mode before any other command is sent to DRAM.
TC_MR4_shaddow_0_0_0_MCHBAR should be updated with the correct value of tCAL
once its value changes.
28
0h
RO
ddr_probeless_low_frequency: This bit controls whether the DDR probeless logic
uses DDR_TX_DELAY_LOW or DDR_TX_DELAY_HIGH for the internal delay of the write
data. If MRC supports two training frequencies, this bit should be set when training at
the low frequency.
27
0h
RO
enable_odt_matrix: When bit is set, the ranks that are used for terminating when
giving read/write requests are selected according to SC_ODT_MATRIX control register
and not according to the default behavior.
26:24
0h
RO
ck_to_cke: When working with LPDDR when CKE is low we also turn off the CKe
buffers. The LPDDR specification requires starting the CK toggling two DCLK cycles
before re-asserting CKE. The field defines the number of DCLK cycles from
CKoutputEnable assert on power down exit to CKE assert as the DDRIO can delay the
CK pins differently than CKE so a different value is required to get two DCLK cycles of
CK toggling before CKE rise. Typically this field should be programmed to 3 if
(CLK_pi+CLK_logicdelay)-(CKE_pi+CKE_logicdelay) is less than 1 QCLK. Otherwise, it
should be programmed to 4 supported range is 2-7.
23
0h
RO
cmd_3st: Defines when command and address bus is driving.
0: Drive when channel is active. Tri-stated when all ranks are in CKE-off or when
memory is in SR or deeper.
1: Command bus is always driving. When no new valid command is driven, previous
command and address is driven
22:20
0h
RO
reset_delay: Inserts an N Dclk delay ranging from 0 to 7 after the N to 1 Reset on
Cmd is triggered.
19:16
0h
RO
reset_on_command: The N:1 logic can be triggered to insert a bubble and reset the
N:1 logic after a programmable delay from a command after a PRE/ACT/RD/WR CMD.
This allows one to synchronize the N:1 logic periodically to ensure the correct worst
case pattern between victim and aggressor occurs when training the command bus.
Reset N to 1 Logic on a WR (bit 16) Reset N to 1 Logic on a RD (bit 17) Reset N to 1
Logic on a ACT (bit 18) Reset N to 1 Logic on a PRE (bit 19)
15
0h
RO
LPDDR_2N_CS_MRW: When sending an MRW command via the MRH for LPDDR,
drive the CSb for two DCLK cycles
14:12
0h
RO
tCPDED: Holds DDR timing parameter tCPDED. Power down to command bus tri-state
delay in DCLK cycles. Supported range is 1-7 in 1N mode.
11:10
0h
RO
x8_device: DIMM is made out of X8 devices LSB is for DIMM 0, MSB is for DIMM 1.
9:8
0h
RO
Address_mirror: DIMM routing causes address mirroring LSB is for DIMM 0, MSB is
for DIMM 1.
6:4
0h
RO
N_to_1_ratio: When using N:1 command stretch mode, every how many B2B valid
command cycles a bubble is required Supported range is 1 to 7
3:2
0h
RO
CMD_stretch: Command stretch mode:
00: 1N
01: 2N
10: 3N
11: N:1
1:0
0h
RO
DRAM_technology: DRAM technology:
00: DDR4
01: DDR3
10: LPDDR3
11: Illegal