Specification Sheet

MCHBAR Registers
170 Datasheet, Volume 2 of 2
7.1 MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR—
Offset 4000h
DDR timing
Access Method
Default: 0h
5948–594Bh 4 GT—Offset 5948h 0h
594C–594Fh 4 EDRAM—Offset 594Ch 0h
5978–597Bh 4 Package—Offset 5978h 0h
597C–597Fh 4 PP0—Offset 597Ch 0h
5980–5983h 4 PP1—Offset 5980h 0h
5994–5997h 4 RP—Offset 5994h FFh
5998–599Bh 4 RP—Offset 5998h 0h
5D10–5D17h 8 SSKPD—Offset 5D10h 0h
5DA8–5DABh 4 BIOS—Offset 5DA8h 0h
5E00h 4 PCU_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PCU—Offset 5E00h 0h
5F3C–5F3Fh 4 CONFIG—Offset 5F3Ch 0h
5F40–5F47h 8 CONFIG—Offset 5F40h 0h
5F48–5F4Fh 8 CONFIG—Offset 5F48h 0h
5F50–5F53h 4 CONFIG—Offset 5F50h 0h
5F54–5F57h 4 TURBO—Offset 5F54h 0h
6200–6203h 4 Package Thermal DPPM Status (PKG)—Offset 6200h 8000000h
6204–6207h 4 Memory Thermal DPPM Status (DDR)—Offset 6204h 0h
Table 7-1. Summary of Bus: 0, Device: 0, Function: 0 (MEM) (Continued)
Offset
Size
(Bytes)
Register Name (Register Symbol) Default Value
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 4000h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
tWRPRE
RSVD
tRDPRE
RSVD
tRAS
tRPab_ext
tRP