Specification Sheet

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Datasheet, Volume 2 of 2 169

MCHBAR Registers

5010–5013h 4 Address decode DIMM parameters (MAD)—Offset 5010h 0h

5034h 4

MCDECS_CR_MRC_REVISION_0_0_0_MCHBAR_MCMAIN—Offset

5034h

5040–5043h 4 Request count from GT (DRAM)—Offset 5040h 0h

5044–5047h 4 Request count from IA (DRAM)—Offset 5044h 0h

5048–504Bh 4 Request count from IO (DRAM)—Offset 5048h 0h

5050–5053h 4 RD data count (DRAM)—Offset 5050h 0h

5054–5057h 4 WR data count (DRAM)—Offset 5054h 0h

5060–5063h 4 Self refresh configuration Register (PM)—Offset 5060h 10200h

5400h 4 NCDECS_CR_GFXVTBAR_0_0_0_MCHBAR_NCU—Offset 5400h 0h

5410h 4 NCDECS_CR_VTDPVC0BAR_0_0_0_MCHBAR_NCU—Offset 5410h 0h

5820–5823h 4 PACKAGE—Offset 5820h 0h

5828–582Fh 8 PKG—Offset 5828h 0h

5830–5837h 8 PKG—Offset 5830h 0h

5838–583Fh 8 PKG—Offset 5838h 0h

5840–5847h 8 PKG—Offset 5840h 0h

5848–584Fh 8 PKG—Offset 5848h 0h

5858–585Fh 8 PKG—Offset 5858h 0h

5880–5883h 4 DDR—Offset 5880h 0h

5884–5887h 4 DRAM—Offset 5884h 3h

5888–588Bh 4 DRAM—Offset 5888h 0h

588C–588Fh 4 DDR—Offset 588Ch 0h

5890–5893h 4 DDR—Offset 5890h FFFFh

5894–5897h 4 DDR—Offset 5894h FFFFh

5898–589Bh 4 DDR—Offset 5898h FFFFh

589C–589Fh 4 DDR—Offset 589Ch FFFFh

58A0–58A3h 4 DDR—Offset 58A0h 0h

58A8–58ABh 4 PACKAGE—Offset 58A8h 7F00h

58B0–58B3h 4 DDR—Offset 58B0h 0h

58B4–58B7h 4 DDR—Offset 58B4h 0h

58C0–58C7h 8 DDR—Offset 58C0h 0h

58C8–58CFh 8 DDR—Offset 58C8h 0h

58D0–58D3h 4 DDR—Offset 58D0h FFFFh

58D4–58D7h 4 DDR—Offset 58D4h FFFFh

58D8–58DBh 4 DDR—Offset 58D8h FFFFh

58DC–58DFh 4 DDR—Offset 58DCh FFFFh

58F0–58F3h 4 PACKAGE—Offset 58F0h 0h

58FC–58FFh 4 IA—Offset 58FCh 0h

5900–5903h 4 GT—Offset 5900h 0h

5918–591Bh 4 SA—Offset 5918h 0h

Table 7-1. Summary of Bus: 0, Device: 0, Function: 0 (MEM) (Continued)

Offset

Size

(Bytes)