Specification Sheet

Datasheet, Volume 2 of 2 167
DMIBAR Registers
6.30 DMI Correctable Error Mask (DMICEMSK)—Offset
1D4h
DMI Correctable Error Mask register. This register is for test and debug purposes only.
Access Method
Default: 2000h
§ §
8
0h
RW1CS
RNRS: REPLAY_NUM Rollover Status:
7
0h
RW1CS
BDLLPS: Bad DLLP Status:
6
0h
RW1CS
BTLPS: Bad TLP Status:
5:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW1CS
RES: Receiver Error Status: Physical layer receiver Error occurred. These errors
include: elastic Buffer Collision, 8b/10b error, De-skew Timeout Error.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 1D4h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
ANFEM
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:14
0h
RO
Reserved (RSVD): Reserved.
13
1h
RWS
ANFEM: Advisory Non-Fatal Error Mask: When set, masks Advisory Non-Fatal errors
from (a) signaling ERR_COR to the device control register, and (b) updating the
Uncorrectable Error Status register.
This register is set by default to enable compatibility with software that does not
comprehend Role-Based Error Reporting.
12:0
0h
RO
Reserved (RSVD): Reserved.