Specification Sheet

Datasheet, Volume 2 of 2 165
DMIBAR Registers
6.28 DMI Uncorrectable Error Severity (DMIUESEV)—
Offset 1CCh
DMI Uncorrectable Error Severity register. This register controls whether an individual
error is reported as a non-fatal or fatal error. An error is reported as fatal when the
corresponding error bit in the severity register is set. If the bit is cleared, the
corresponding error is considered nonfatal. It is for test and debug purposes only.
Access Method
Default: 60010h
11:5
0h
RO
Reserved (RSVD): Reserved.
4
0h
RWS
DLPEM: Data Link Protocol Error Mask:
3:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 1CCh
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
RSVD
ECCERRS
RSVD
URES
ECRCES
MTLPES
ROEV
UCES
CAES
CTES
FCPES
PTLPES
RSVD
DLPES
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:23
0h
RO
Reserved (RSVD): Reserved.
22
0h
RWS
ECCERRS: 2 Bit Error Mask:
21
0h
RO
Reserved (RSVD): Reserved.
20
0h
RWS
URES: Unsupported Request Error Severity:
19
0h
RO
ECRCES: Reserved for ECRC Error Severity:
18
1h
RWS
MTLPES: Malformed TLP Error Severity:
17
1h
RWS
ROEV: Receiver Overflow Error Severity: