Specification Sheet

DMIBAR Registers
158 Datasheet, Volume 2 of 2
6.22 Link Control (LCTL)—Offset 88h
Allows control of PCI Express link.
Access Method
Default: 0h
Type: MEM
(Size: 16 bits)
Offset: [B:0, D:0, F:0] + 88h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
HAWD
RSVD
ES
RSVD
RL
RSVD
ASPM
Bit
Range
Default &
Access
Field Name (ID): Description
15:10
0h
RO
Reserved (RSVD): Reserved.
9
0h
RO
HAWD: OPI - N/A Hardware Autonomous Width Disable: Hardware Autonomous Width
Disable - When Set, this bit disables hardware from changing the Link width for
reasons other than attempting to correct unreliable Link operation by reducing Link
width.
Devices that do not implement the ability autonomously to change Link width are
permitted to hardwire this bit to 0b.
8
0h
RO
Reserved (RSVD): Reserved.
7
0h
RW
ES: OPI - N/A Extended Synch: Extended synch
0: Standard Fast Training Sequence (FTS).
1: Forces the transmission of additional ordered sets when exiting the L0s state and
when in the Recovery state.
This mode provides external devices (e.g., logic analyzers) monitoring the Link time to
achieve bit and symbol lock before the link enters L0 and resumes communication.
This is a test mode only and may cause other undesired side effects such as buffer
overflows or underruns.
6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
RL: Retrain Link:
0: Normal operation.
1: Full Link retraining is initiated by directing the Physical Layer LTSSM from L0, L0s,
or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared automatically (no need to write
a 0).
4:2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
RO
ASPM: Active State PM: Controls the level of active state power management
supported on the given link.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Supported
11: L0s and L1 Entry Supported