Specification Sheet

Datasheet, Volume 2 of 2 155
DMIBAR Registers
6.19 DMI Link Entry 2 Description (DMILE2D)—Offset
60h
First part of a Link Entry which declares an internal link to another Root Complex
Element.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0h
RO
Reserved (RSVD): Reserved.
7:0
0h
RW_O
ULA: Upper Link Address: Memory mapped base address of the RCRB that is the
target element (egress port of PCH) for this link entry.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 60h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPN
TCID
RSVD
LTYP
LV
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0h
RO
TPN: Target Port Number: Specifies the port number associated with the element
targeted by this link entry (Egress Port). The target port number is with respect to the
component that contains this element as specified by the target component ID.
23:16
0h
RW_O
TCID: Target Component ID: Identifies the physical or logical component that is
targeted by this link entry.
BIOS Requirement: should be initialized according to guidelines in the PCI Express*
Isochronous/Virtual Channel Support Hardware Programming Specification (HPS).
15:2
0h
RO
Reserved (RSVD): Reserved.
1
0h
RO
LTYP: Link Type: Indicates that the link points to memory-mapped space (for RCRB).
The link address specifies the 64-bit base address of the target RCRB.
0
0h
RW_O
LV: Link Valid:
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.