Specification Sheet

Datasheet, Volume 2 of 2 153
DMIBAR Registers
6.16 DMI Link Entry 1 Description (DMILE1D)—Offset
50h
First part of a Link Entry which declares an internal link to another Root Complex
Element.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 50h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPN
TCID
RSVD
LTYP
LV
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0h
RW_O
TPN: Target Port Number: Specifies the port number associated with the element
targeted by this link entry (egress port of PCH). The target port number is with respect
to the component that contains this element as specified by the target component ID.
This can be programmed by BIOS, but the default value will likely be correct because
the DMI RCRB in the PCH will likely be associated with the default egress port for the
PCH meaning it will be assigned port number 0.
23:16
0h
RW_O
TCID: Target Component ID: Identifies the physical component that is targeted by
this link entry.
BIOS Requirement: should be initialized according to guidelines in the PCI Express*
Isochronous/Virtual Channel Support Hardware Programming Specification (HPS).
15:2
0h
RO
Reserved (RSVD): Reserved.
1
0h
RO
LTYP: Link Type: Indicates that the link points to memory-mapped space (for RCRB).
The link address specifies the 64-bit base address of the target RCRB.
0
0h
RW_O
LV: Link Valid:
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.