Specification Sheet

Datasheet, Volume 2 of 2 143
DMIBAR Registers
6.6 DMI VC0 Resource Control (DMIVC0RCTL)—Offset
14h
Controls the resources associated with PCI Express Virtual Channel 0.
Access Method
Default: 8000017Fh
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 14h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1
VC0E
RSVD
VC0ID
RSVD
PAS
RSVD
FC_FSM_STATE
TCMVC0M
TCVC0M
TC0VC0M
Bit
Range
Default &
Access
Field Name (ID): Description
31
1h
RO
VC0E: Virtual Channel 0 Enable: For VC0 this is hardwired to 1 and read only as VC0
can never be disabled.
30:27
0h
RO
Reserved (RSVD): Reserved.
26:24
0h
RO
VC0ID: Virtual Channel 0 ID: Assigns a VC ID to the VC resource. For VC0 this is
hardwired to 0 and read only.
23:20
0h
RO
Reserved (RSVD): Reserved.
19:17
0h
RW
PAS: Port Arbitration Select: Configures the VC resource to provide a particular Port
Arbitration service. Valid value for this field is a number corresponding to one of the
asserted bits in the Port Arbitration Capability field of the VC resource. Because only
bit 0 of that field is asserted.
This field will always be programmed to '1'.
16:13
0h
RO
Reserved (RSVD): Reserved.
12:8
1h
ROV
FC_FSM_STATE: This register is for Save Restore to restore the FC fsm
7
0h
RO
TCMVC0M: Traffic Class m / Virtual Channel 0 Map:
6:1
3Fh
RW
TCVC0M: Traffic Class / Virtual Channel 0 Map: Indicates the TCs (Traffic Classes) that
are mapped to the VC resource. Bit locations within this field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. When
more than one bit in this field is set, it indicates that multiple TCs are mapped to the
VC resource. In order to remove one or more TCs from the TC/VC Map of an enabled
VC, software should ensure that no new or outstanding transactions with the TC labels
are targeted at the given Link.
0
1h
RO
TC0VC0M: Traffic Class 0 / Virtual Channel 0 Map: Traffic Class 0 is always routed to
VC0.