Specification Sheet

Datasheet, Volume 2 of 2 137
Dynamic Power Performance Management (DPPM) Registers
§ §
19
0h
RO
Reserved (RSVD): Reserved.
18
0h
RO_V
ADDGFXEN:
0: Additive Graphics Disabled
1: Additive Graphics Enabled
17
0h
RO_V
ADDGFXCAP:
0: Capable of Additive Graphics
1: Not capable of Additive Graphics
16
0h
RO
Reserved (RSVD): Reserved.
15
0h
RO_V
DMIG3DIS: DMI Gen 3 Disable fuse.
14:9
0h
RO
Reserved (RSVD): Reserved.
8
0h
RO_V
GMM_DIS:
0: Device 8 associated memory spaces are accessible.
1: Device 8 associated memory and IO spaces are disabled by hardwiring the D8EN
field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to '0'.
7
0h
RO
Reserved (RSVD): Reserved.
6:4
0h
RO_V
DMFC_DDR3: This field controls which values may be written to the Memory
Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset
C00h). Any attempt to write an unsupported value will be ignored.
000: MC capable of DDR3 2667 (2667 is the upper limit)
001: MC capable of up to DDR3 2667
010: MC capable of up to DDR3 2400
011: MC capable of up to DDR3 2133
100: MC capable of up to DDR3 1867
101: MC capable of up to DDR3 1600
110: MC capable of up to DDR3 1333
111: MC capable of up to DDR3 1067
3
0h
RO
Reserved (RSVD): Reserved.
2
0h
RO_V
LPDDR3_EN: Allow LPDDR3 operation
1:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description