Specification Sheet

12 Datasheet, Volume 2 of 2
14.3 PCI Command (PCICMD)—Offset 4h ...................................................................452
14.4 PCI Status (PCISTS)—Offset 6h .........................................................................453
14.5 Revision Identification (RID)—Offset 8h ..............................................................455
14.6 Class Code (CC)—Offset 9h ...............................................................................455
14.7 Cache Line Size (CL)—Offset Ch.........................................................................456
14.8 Header Type (HDR)—Offset Eh ..........................................................................456
14.9 Primary Bus Number (PBUSN)—Offset 18h ..........................................................457
14.10 Secondary Bus Number (SBUSN)—Offset 19h ......................................................457
14.11 Subordinate Bus Number (SUBUSN)—Offset 1Ah..................................................458
14.12 I/O Base Address (IOBASE)—Offset 1Ch .............................................................458
14.13 I/O Limit Address (IOLIMIT)—Offset 1Dh ............................................................459
14.14 Secondary Status (SSTS)—Offset 1Eh ................................................................460
14.15 Memory Base Address (MBASE)—Offset 20h ........................................................461
14.16 Memory Limit Address (MLIMIT)—Offset 22h .......................................................461
14.17 Prefetchable Memory Base Address (PMBASE)—Offset 24h ....................................462
14.18 Prefetchable Memory Limit Address (PMLIMIT)—Offset 26h....................................463
14.19 Prefetchable Memory Base Address Upper (PMBASEU)—Offset 28h .........................464
14.20 Prefetchable Memory Limit Address Upper (PMLIMITU)—Offset 2Ch ........................465
14.21 Capabilities Pointer (CAPPTR)—Offset 34h ...........................................................466
14.22 Interrupt Line (INTRLINE)—Offset 3Ch................................................................466
14.23 Interrupt Pin (INTRPIN)—Offset 3Dh...................................................................467
14.24 Bridge Control (BCTRL)—Offset 3Eh ...................................................................467
14.25 Power Management Capabilities (PM)—Offset 80h ................................................469
14.26 Power Management Control/Status (PM)—Offset 84h ............................................470
14.27 Subsystem ID and Vendor ID Capabilities (SS)—Offset 88h ...................................471
14.28 Subsystem ID and Subsystem Vendor ID (SS)—Offset 8Ch....................................472
14.29 Message Signaled Interrupts Capability ID (MSI)—Offset 90h.................................473
14.30 Message Control (MC)—Offset 92h .....................................................................473
14.31 Message Address (MA)—Offset 94h ....................................................................474
14.32 Message Data (MD)—Offset 98h ........................................................................475
14.33 PCI Express-G Capability List (PEG)—Offset A0h ..................................................475
14.34 PCI Express-G Capabilities (PEG)—Offset A2h ......................................................476
14.35 Device Capabilities (DCAP)—Offset A4h...............................................................476
14.36 Device Control (DCTL)—Offset A8h.....................................................................477
14.37 Device Status (DSTS)—Offset AAh .....................................................................478
14.38 Link Capability (LCAP)—Offset ACh.....................................................................479
14.39 Link Control (LCTL)—Offset B0h.........................................................................481
14.40 Link Status (LSTS)—Offset B2h..........................................................................482
14.41 Slot Capabilities (SLOTCAP)—Offset B4h .............................................................484
14.42 Slot Control (SLOTCTL)—Offset B8h ...................................................................485
14.43 Slot Status (SLOTSTS)—Offset BAh ....................................................................487
14.44 Root Control (RCTL)—Offset BCh........................................................................488
14.45 Root Status (RSTS)—Offset C0h ........................................................................489
14.46 Device Capabilities 2 (DCAP2)—Offset C4h ..........................................................490
14.47 Device Control 2 (DCTL2)—Offset C8h ................................................................492
14.48 Link Control 2 (LCTL2)—Offset D0h ....................................................................493
14.49 Link Status 2 (LSTS2)—Offset D2h .....................................................................495
14.50 Port VC Capability Register 1 (PVCCAP1)—Offset 104h ..........................................496
14.51 Port VC Capability Register 2 (PVCCAP2)—Offset 108h ..........................................497
14.52 Port VC Control (PVCCTL)—Offset 10Ch ..............................................................497
14.53 VC0 Resource Capability (VC0RCAP)—Offset 110h................................................498
14.54 VC0 Resource Control (VC0RCTL)—Offset 114h....................................................499
14.55 VC0 Resource Status (VC0RSTS)—Offset 11Ah ....................................................500
14.56 PEG Uncorrectable Error Status—Offset 1C4h ......................................................501
14.57 PEG Uncorrectable Error Mask—Offset 1C8h ........................................................502