Specification Sheet

Processor Graphics Registers
132 Datasheet, Volume 2 of 2
4.33 Power Management Control/Status (PMCS)—
Offset D4h
Access Method
Default: 0h
§ §
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + D4h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMESTS
DSCALE
DSEL
PMEEN
RSVD
PWRSTAT
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RO
PMESTS: This bit is 0 to indicate that Processor Graphics does not support PME#
generation from D3 (cold).
14:13
0h
RO
DSCALE: The Processor Graphics does not support data register. This bit always
returns 00 when read, write operations have no effect.
12:9
0h
RO
DSEL: The Processor Graphics does not support data register. This bit always returns
0h when read, write operations have no effect.
8
0h
RO
PMEEN: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
7:2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
RO_V
PWRSTAT: This field indicates the current power state of the Processor Graphics and
can be used to set the Processor Graphics into a new power state. If software attempts
to write an unsupported state to this field, write operation should complete normally
on the bus, but the data is discarded and no state change occurs. On a transition from
D3 to D0 the graphics controller is optionally reset to initial values.
Bits[1:0] Power state
00: D0 Default
01: D1 Not Supported
10: D2 Not Supported
11: D3