Specification Sheet

Datasheet, Volume 2 of 2 131
Processor Graphics Registers
4.32 Power Management Capabilities (PMCAP)—Offset
D2h
This register provides information on the capabilities of the function related to power
management.
Access Method
Default: 22h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:2, F:0] + D2h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
PMES
D2 D1
RSVD
DSI
RSVD
PMECLK
VER
Bit
Range
Default &
Access
Field Name (ID): Description
15:11
0h
RO
PMES: This field indicates the power states in which the Processor Graphics may
assert PME#. Hardwired to 0 to indicate that the Processor Graphics does not assert
the PME# signal.
10
0h
RO
D2: The D2 power management state is not supported. This bit is hardwired to 0.
9
0h
RO
D1: Hardwired to 0 to indicate that the D1 power management state is not supported.
8:6
0h
RO
Reserved (RSVD): Reserved.
5
1h
RO
DSI: Hardwired to 1 to indicate that special initialization of the Processor Graphics is
required before generic class device driver is to use it.
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PMECLK: Hardwired to 0 to indicate Processor Graphics does not support PME#
generation.
2:0
2h
RO
VER: Hardwired to 010b to indicate that there are 4 bytes of power management
registers implemented and that this device complies with revision 1.1 of the PCI Power
Management Interface Specification.